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XRT4000 universal multiprotocol serial interface november 1998-2 rev. 1.00 exar corporation, 48720 kato road, fremont, ca 95538 (510) 668-7000 fax (510) 668-7017 features software-configurable multiprotocol serial interface supporting: v.35, v.36, eia-530 (a), rs232 (v.28), x.21, rs449 one chip fully integrated solution (internal termination) contains 8 receivers and 8 transmitters for full dte and dce support glitch filters on the control signals (optional) +5v, +12v, -6v power supplies required full support of loopbacks, data & clock inversion, and echoed clock in dte and dce modes full support of most popular types of hdlc controllers (single, double, and triple clocks supported) internal oscillator for standalone dte loopback testing control signals can be registered and non- registered control signals can be tri-stated for bus-based designs fail safe operation supported esd protection over + 2kv range applications data service units (dsu) routers access multiplexers general description the XRT4000 is a fully integrated multiprotocol serial interface. it is a universal device because it supports all of the popular serial physical interfaces such as v.35, v.36, eia-530 (a), rs232 (v.28), x.21 and rs449. furthermore it can easily be interfaced with most common types of hdlc controllers. this device contains 8 receivers and 8 transmitters. it is a complete solution containing all of the required source and load terminations in one 100 pin tqfp package. XRT4000 can be configured to operate in one of the seven interfaces in either dte and dce modes of operation and power down mode. it fully supports echoed clock as well as clock and data inversion. an elaborate set of loopbacks are supported in dte and dce modes of operation. this eliminates the need for external circuitry for loopback implementation. the control signals such as ri, rl, dcd, dtr, dsr are protected against glitches by internal filters. these filters can be disabled. XRT4000 has an internal oscillator which is used to create a clock signal needed to conduct standalone diagnostics of dte equipment. order information part no. package operating temperature range XRT4000cv 100 pin tqfp 0 c to +70 c
XRT4000 rev. 1.00 - 2 - figure 1. xrt 4000 functional block diagram
XRT4000 rev. 1.00 - 3 - figure 2. xrt 4000 rtmod1 block figure 3. xrt 4000 rtmod2 block
XRT4000 rev. 1.00 - 4 - figure 4. xrt 4000 rtmod3 block figure 5. xrt 4000 control block note: signals without pin numbers having names identical to those with pin numbers are cmos level-shifted versions of ttl-compatible input signals.
XRT4000 rev. 1.00 - 5 - pin configuration vdd gnd m0 m2 en_fltr en_term latch* vss vss gnd clkfs m1 tx4d vdd tx4b tx5a tx4a tx5b tx8d gnd tx5d tx8o vss lp* vdd tx1d gnd vss vdd gnd vss dtinv* ckinv* en_osc* 2ck/3ck* reg_clk vdd vr vpp nc nc nc nc e_232h* vpp vdd n/c gnd vss n/c en_out* vss vdd vdd rx8d gnd rx8i tr7 vss tx76d tr6a tr6b dce/dte* rx67d rx5d ec* rx5b rx5a rx4a rx4b slew_cntl rx4d gnd n/c reg rx1d vdd rx1b rx1a rx2a rx2b vss rx2d vdd gnd rx3d gnd tr3b tr3a cm_tr3 vss tx3d vdd tx2d cm_tx2 tx2b tx2a tx1a tx1b cm_tx1 60 30 40 50 80 90 10 20 70 100-pin tqfp XRT4000
XRT4000 rev. 1.00 - 6 - pin description pin # symbol dte mode dce mode type function 1vdd digital vdd for receiver 1 - connect to +5v 2gnd digital gnd for receiver 1 3m0 i mode control - mode select input 0; internal 20k w pull-up 4m1 i mode control - mode select input 1; internal 20k w pull-up 5m2 i mode control - mode select input 2; internal 20k w pull-up 6 en_fltr i enable glitch filter on receiver 4, 5, 6, 7, 8 inputs. internal 20k w pull-down 7 en_term i enable input termination for receiver 1, 2, 3 in v.11 mode. internal 20k w pull-down 8 latch* i mode control input latch enable - logic 0 : changes on m0, 1, 2, en_fltr, and en_term pins cause mode changes (input latches in transparent state). logic 1 : changes on these input pins do not cause mode changes (input latches in latched state). internal 20k w pull- down 9 vss digital vss for transmitter 4, 5, 6. connect to -6v 10 vss analog vss for bias generation connect to -6v 11 gnd digital gnd for transmitter 7, 8 12 clkfs o internal clock generated - 500khz 13 tx4d d_rts d_cts i transmitter 4 - digital data input from equipment 14 vdd digital vdd for transmitter 4, 5, 6; connect to +5v 15 tx4b rtsb ctsb o transmitter 4 - positive data differential output to line 16 tx4a rtsa ctsa o transmitter 4 - negative data differential output to line 17 tx5a dtra dsra o transmitter 5 - negative data differential output to line 18 tx5b dtrb dsrb o transmitter 5 - positive data differential output to line 19 gnd digital gnd for transmitter 4, 5, 6 20 tx5d d_dtr d_dsr i transmitter 5 - digital data input from equipment 21 tx8d d_rl d_ri i transmitter 8 - digital data input from equipment 22 lp* i loopback enable - active low; logic 0 : loopback enabled. logic 1 : loopback disabled. internal 20k w pull-up 23 tx8o rla ria o transmitter 8 - single ended data output to line 24 vss digital vss for transmitter 7, 8; connect to -6v 25 vdd digital vdd for transmitter 7, 8; connect to +5v 26 en_out* i output enable for receiver 5, 8; internal 20k w pull-down 27 reg i register control - logic 1 : tx5d, tx8d signal values will be latched on the positive edge of reg_clk, logic 0: the register flip-flop is bypassed therefore reg_clk has no effect on these signals. internal 20k w pull-down 28 vss analog vss for receiver 4, 5, 6; connect to -6v 29 vdd analog vdd for receiver 4, 5, 6; connect to +5v 30 vdd analog vdd for receiver 7, 8; connect to +5v 31 rx8d d_ri d_rl o receiver 8 - digital data output to equipment 32 gnd analog gnd for receiver 7, 8 33 rx8i ria rla i receiver 8 - single ended data input from line 34 vss analog vss for receiver 7, 8; connect to -6v note: an asterisk (*) following a pin symbol indicates that the pin is active low. names begining with d_ are digital signals. names ending with b and a are the positive and negative polarities of differential signals respectively.
XRT4000 rev. 1.00 - 7 - pin description (contd) pin # symbol dte mode dce mode type function 35 tr7 lla lla i/o dte mode - transmitter 7 - single ended data output to line dce mode - receiver 7 - single ended data input from line 36 tx76d d_ll d_dcd i digital input - refer to mode control table 37 tr6a dcda dcda i/o dte mode - receiver 6 - negative data differential input from line dce mode - transmitter 6 - negative data differential output to line 38 tr6b dcdb dcdb i/o dte mode - receiver 6 - positive data differential input from line dce mode - transmitter 6 - positive data differential output to line 39 dce/dte* low high i dce/dte select - selects operating mode . logic 0 : dte mode. logic 1 : dce mode. internal 20k w pull-up 40 rx67d d_dcd d_ll o digital output - refer to mode control table 41 rx5d d_dsr d_dtr o receiver 5 - digital data output to equipment 42 ec* i enable clock mode - active low, logic 0 : echoed mode. logic 1 : normal mode. internal 20k w pull-up 43 rx5b dsrb dtrb i receiver 5 - positive data differential input from line 44 rx5a dsra dtra i receiver 5 - negative data differential input from line 45 rx4a ctsa rtsa i receiver 4 - negative data differential input from line 46 rx4b ctsb rtsb i receiver 4 - positive data differential input from line 47 slew_ cntl o analog output - resistor connected between this pin and ground controls transmitter output pulse rise and fall time in v.10 or v.28 mode as specified in figures 15 and 16 respectively. 48 rx4d d_cts d_rts o receiver 4 - digital data output to equipment 49 gnd digital gnd for receiver 4, 5, 6 50 nc 51 nc 52 gnd analog gnd for bias generator. 53 nc 54 vss analog substrate - connect to -6v 55 e_232h* i high speed rs-232 enable - logic 0: enables high speed rs-232 mode (drives 3k w in parallel with 1000pf at 256khz). internal 20k w pull-up 56 vdd analog vdd for bias generation circuit; connect to +5v 57 vpp vpp - connect to +12v supply 58 nc 59 nc 60 nc 61 nc 62 vpp vpp - connect to +12v supply 63 vr o vr - internally generated +2.2v reference (sources 20 m a maximum) note: an asterisk (*) following a pin symbol indicates that the pin is active low. names begining with d_ are digital signals. names ending with b and a are the positive and negative polarities of differential signals respectively
XRT4000 rev. 1.00 - 8 - pin # symbol dte mode dce mode type function 64 reg_clk i clock - for transmitter 5, 8 input register. internal 20k w pull-up 65 2ck/3ck* i 2 or 3 clock select - internal 20k w pull-up logic dont care : 1 clock when mode = x.21 (m2, m1, m0= 011) logic 0 : 3 clocks when mode 1 x.21 (m2, m1, m0 1 011) logic 1 : 2 clocks when mode 1 x.21 (m2, m1, m0 1 011) 66 en_osc* i test oscillator enable - active low; logic 0: oscillator enabled. logic 1 : oscillator disabled. internal 20k w pull-up 67 ckinv* i invert clock - active low; logic 0 : clock inverted. logic 1 : clock not inverted. internal 20k w pull-up 68 dtinv* i invert data - active low; logic 0 : data inverted. logic 1 : data not inverted. internal 20k w pull-up 69 vss digital vss for transmitter 1, 2, 3 output drivers; connect to -6v 70 gnd digital gnd for transmitter 1, 2, 3 output drivers 71 vdd digital vdd for transmitter 1, 2, 3 output drivers; connect to +5v 72 vdd analog vdd for transmitter 1, 2; connect to +5v 73 vss analog vss for transmitter 1, 2; connect to -6v 74 gnd analog gnd for transmitter 1, 2 t termination 75 tx1d d_txd d_rxd i transmitter 1 - digital data input from equipment 76 cm_tx1 o ac gnd - transmitter 1 output termination center tap in v.35 mode 77 tx1b txdb rxdb o transmitter 1 - positive data differential output to line 78 tx1a txda rxda o transmitter 1 - negative data differential output to line 79 tx2a sctea rxca o transmitter 2 - negative data differential output to line 80 tx2b scteb rxcb o transmitter 2 - positive data differential output to line 81 cm_tx2 o ac gnd - transmitter 2 output termination center tap in v.35 mode 82 tx2d d_scte d_rxc i transmitter 2 - digital data input from equipment 83 vdd digital vdd for receiver and transmitter 1, 2, 3; connect to +5v 84 tx3d d_x d_txc i dte mode - input not used dce mode - transmitter 3 - digital data input from equipment 85 vss digital vss for receiver and transmitter 1, 2, 3; connect to -6v 86 cm_tr3 o dte mode - ac gnd - transmitter 3 output termination center tap in v.35 mode dce mode - ac gnd - receiver 3 input termination center tap in v.35 mode 87 tr3a txca txca i/o dte mode - receiver 3 - negative data differential input from line. dce mode - transmitter 3 - negative data differential output to line. note: an asterisk (*) following a pin symbol indicates that the pin is active low. names begining with d_ are digital signals. names ending with b and a are the positive and negative polarities of differential signals respectively
XRT4000 rev. 1.00 - 9 - pin # symbol dte mode dce mode type function 88 tr3b txcb txcb i/o dce mode - transmitter 3 - positive data differential output to line dte mode - receiver 3 - positive data differential input from line 89 gnd analog gnd for receiver 1, 2, 3 90 rx3d d_txc d_x o dte mode - receiver 3- digital data output to equipment dce mode - not used 91 vdd digital vdd for receiver 2, 3; connect to +5v 92 gnd digital gnd for receiver 2, 3 93 rx2d d_rxc d_scte o receiver 2 - digital data output to equipment 94 vss analog vss for receiver 1, 2, 3; connect to -6v 95 rx2b rxcb scteb i receiver 2 - positive data differential input from line 96 rx2a rxca sctea i receiver 2 - negative data differential input from line 97 rx1a rxda txda i receiver 2 - negative data differential input from line 98 rx1b rxdb txdb i receiver 2 - positive data differential input from line 99 vdd analog vdd for receiver 1, 2, 3; connect to +5v 100 rx1d d_rxd d_txd o receiver 1 - digital data output to equipment note: an asterisk (*) following a pin symbol indicates that the pin is active low. names begining with d_ are digital signals. names ending with b and a are the positive and negative polarities of differential signals respectively. `
XRT4000 rev. 1.00 - 10 - electrical charcteristics test conditions: vdd = 5v, vss = -6v, vpp = 12v (all 5%), ta = 25 c sybol parameter min typ max unitd interface supply currents m0 m1 m2 i dd vdd supply current 20 ma 0 0 0 v.10, no load (dce mode, 90 ma 0 0 0 v.10, full load all digital pins=gnd 20 ma 1 0 0 eia-530a, no load or vdd) 160 ma 1 0 0 eia-530a, full load 55 ma 0 0 1 v.35, no load on v.28 drivers 55 ma 0 0 1 v.35, full load on v.28 drivers 16 ma 0 1 1 rs232, no load 16 ma 0 1 1 rs232, full load 2 ma 1 1 1 power down mode i ss vss supply current 30 ma 0 0 0 v.10, no load (dce mode, 90 ma 0 0 0 v.10, full load all digital pins=gnd 30 ma 1 0 0 eia-530a, no load or vdd) 50 ma 1 0 0 eia-530a, full load 45 ma 0 0 1 v.35, no load on v.28 drivers 55 ma 0 0 1 v.35, full load on v.28 drivers 16 ma 0 1 1 rs232, no load 30 ma 0 1 1 rs232, full load 2 ma 1 1 1 power down mode i pp vpp supply current 10 ma 0 0 0 v.10, no load (dce mode, 10 ma 0 0 0 v.10, full load all digital pins = gnd 10 ma 1 0 0 eia-530a, no load or vdd) 10 ma 1 0 0 eia-530a, full load 10 ma 0 0 1 v.35, no load on v.28 drivers 20 ma 0 0 1 v.35, full load on v.28 drivers 10 ma 0 1 1 rs232, no load 25 ma 0 1 1 rs232, full load 10 ma 1 1 1 power down mode note 1: absolute maximum ratings are those beyond which the safety of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device are negative. all voltages are referenced to device ground unless otherwise specified.
XRT4000 rev. 1.00 - 11 - electrical charcteristics (contd) test conditions: vdd = 5v, vss = -6v, vpp = 12v (all 5%), ta = 25 c symbol parameter min typ max units conditions logic inputs and outputs v ih logic input high voltage 2v v il logic input low voltage 0.8 v i in logic input current 250 m a with 20k w internal pull-up/down resistor v oh output high voltage 3 4.5 v io = -4ma v ol output low voltage 0.3 0.8 v io = 4ma i osr output short- circuit current -60 60 ma 0v vo vdd i ozr three-state output current 01 m a m0 = ml = m2 = vdd 0v vo vdd v.11 driver v od differential output voltage 2 5 v open circuit rl = 50 w (figure 6) d v od change in magnitude of differential output voltage 0.2 v rl = 50 w (figure 6) v oc common mode output voltage 3.0 v rl = 50 w (figure 6) d v oc change in magnitude of common mode output voltage 0.2 v rl = 50 w (figure 6) i ss short-circuit current 150 ma vo = gnd i oz output leakage current 0.01 100 m a -0.25v vo 0.25v, power off or driver disabled t r , t f rise or fall time 4 13 25 ns (figures 7, 11) t plh input to output 50 70 110 ns (figures 7, 11) t phl input to output 50 70 110 ns (figures 7, 11) d t inp. to out. difference, |tplh - tphl| 0 5 15 ns (figures 7, 11) t skew output to output skew 5 ns (figures 7, 11) note 1: absolute maximum ratings are those beyond which the safety of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device are negative. all voltages are referenced to device ground unless otherwise specified.
XRT4000 rev. 1.00 - 12 - electrical charcteristics (contd) test conditions: vdd = 5v, vss = -6v, vpp = 12v (all 5%), ta = 25 c symbol parameter min typ max units conditions v.11 receiver v th input threshold voltage -0.2 0.2 -7v vcm 7v d vth input hysteresis 35 60 mv -7v vcm 7v i in input current (a, b) 1 1.5 ma -10v va,b 10v r in input impedance 9 10 11 k w -10v va,b 10v t r , t f rise or fall time 20 ns (figures 7, 12) t plh input to output 50 80 120 ns (figures 7, 12) t phl input to output 50 80 120 ns (figures 7, 12) d t inp. to out. difference, |tplh - tphl| 0 5 15 ns (figures 7, 12) v.35 driver v od differential output voltage 0.44 0.55 0.66 v with load, (figure 12) i oh transmitter output high current -12 -11 -10 ma va, b = 0v i ol transmitter output low current 10 11 12 ma va, b = 0v i oz transmiter output leakage current 0.01 100 m a -0.25 va,b 0.25v t r , t f rise or fall time 5 ns (figures 8, 11) t plh input to output 25 55 85 ns (figures 8, 11) t phl input to output 25 55 85 ns (figures 8, 11) d t inp. to out. difference, |tplh - tphl| 0 5 15 ns (figures 8, 11) t skew output to output skew 5 ns (figures 8, 11) v.35 receiver v th differential input threshold volt. -0.2 0.2 v -2v = (va + vb)/2 = 2v (figure 8) d v th input hysteresis 35 60 mv -2v = (va + vb)/2 = 2v (figure 8) i in input current (a,b) 60 ma -10v = va, b = 10v r in input impedance (a, b) 175 w -10v = va, b = 10v t r , t f rise or fall time 20 ns (figures 8, 12) t plh input to output 80 120 ns (figures 8, 12) t phl input to output 100 120 ns (figures 8, 12) d t input to output difference, itplh - tphli 5 15 ns (figures 8, 12) note 1: absolute maximum ratings are those beyond which the safety of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device are negative. all voltages are referenced to device ground unless otherwise specified.
XRT4000 rev. 1.00 - 13 - electrical charcteristics (contd) test conditions: vdd = 5v, vss = -6v, vpp = 12v (all 5%), ta = 25 c symbol parameter min typ max units conditions v.10 driver v o output voltage 4.0 3.6 6.0 v v open circuit, rl = 3.9k rl = 450 w (figure 9) i ss short-circuit current 100 ma vo = gnd i oz input leakage current 0.1 100 m a -0.25 vo 0.25v, power off or driver disabled t r , t f rise or fall time 05 m s (figures 9, 13), rl = 450 w , cl = 100pf rslew_cntl = 10k t plh input to output 5 m s (figures 9, 13), rl = 450 w , cl = 100pf rslew_cntl = 10k t phl input to output 5 m s (figures 9, 13), rl = 450 w , cl = 100pf rslew_cntl = 10k v.10 receiver v th receiver input threshold voltage -0.2 0.2 v av th receiver input hysteresis 35 60 mv i in receiver input current 1 1.5 ma -10 va 10v r in receiver input impedance 91011 k w -10 va 10v t r , t f rise or fall time 20 ns (figures 10, 14) t plh input to output 100 ns (figures 10, 14) t phl input to output 100 ns (figures 10, 14) v.28 driver v o output voltage 5 5.5 6 v open circuit rl = 3k (figure 9) i ss short-circuit current 100 ma vo = gnd i oz input leakage current 0.01 100 m a -0.25 vcm 0.25v, power off or driver disabled sr slew rate 4.0 30.0 v/ m s (figures 9, 13), rl = 3k, cl = 2500pf t plh input to output 2 4 m s (figures 9, 13), rl = 3k, cl = 2500pf t phl input to output 2 4 m s (figures 9, 13), rl = 3k, cl = 2500pf v.28 receiver v thl input low threshold voltage 1.4 0.8 v v tlh input high threshold voltage 2.0 1.4 v av th receiver input hysteresis 0.1 0.4 1.0 v r in receiver input impedance 357 k w -15 va 15v t r , t f rise or fall time 20 ns (figures 10, 14) t plh input to output 120 ns (figures 10, 14) t phl input to output 180 ns (figures 10, 14)
XRT4000 rev. 1.00 - 14 - the following tests circuits and timing diagrams are referenced in the preceding electrical characteristics tables. figure 6. rs 422 driver test circuit figure 7. rs 422 driver/receiver ac test circuit figure 8. v.35 dri ver/receiver ac test circuit (tx1/rx1, tx2/rx2 only) figure 9. v.10/v.28 dri ver test circuit figure 10. v.10/v.28 receiver test circuit
XRT4000 rev. 1.00 - 15 - figure 11. v.11, v.35 dri ver propagat ion delays v1 = 0v for v.35, 2.5v for v.11 figure 12. v.11, v.35 receiver propagat ion delays figure 13. v.10, v.28 dri ver propagat ion delays v1 = 1.8v for v.28, 0.1v for v.10 v2 = 1.0v for v.28. -0.1v for v.10 figure 14. v.10, v.28 receiver propagat ion delays
XRT4000 rev. 1.00 - 16 - system description it is important to describe the difference between an electrical specification and a physical interface specification. an electrical specification defines the electrical characteristics of a transmitter or receiver. these include voltage, current, impedance levels, rise/fall times and other similar parameters. popular electrical interfaces are v.10, v.11, v.35 and v.28. a serial physical interface specification, however, describes an interface in its entirety. this description includes the names and functions of all involved signals, the electrical parameters of each of the signals, and the connector type. popular serial interface types include v.35, rs232 (v.28), rs449, eia-530(a), x.21, and v.36. the XRT4000 contains a sufficient number of receivers, transmitters and transceivers to transport all of the signals required for a physical serial interface. it has control circuitry that can configure each driver and receiver to the appropriate electrical levels required by the specification for the selected serial interface. figure 1 is a top level block diagram that shows how the eight receivers and eight transmitters present in the XRT4000 are grouped in three modules named rtmod1, rtmod2, and rtmod3. a forth module labeled control programs these receivers and transmitters with the appropriate electrical levels for operation with most popular standard serial interfaces such as v.35, rs232, rs449, eia-530(a), x.21, and v.36. these interfaces are fully compliant with international net1 and net2 specifications. figures 2, 3, 4, and 5 are a set of functional block diagrams that give more detailed information about the four modules shown in the top-level diagram. the eight receivers and transmitters are grouped in three different categories according to the type of signals transmitted or received. the categories are denoted as rtmod1 (figure 2), rtmod2 (figure 3), rtmod3 (figure 4), and control (figure 5). rtmod1 block rtmod1 is intended for the high speed data and clock signals of a selected interface. this block contains receivers rx1 and rx2, transmitters tx1 and tx2, and bi-directional transceiver tr3 which is composed of tx3 and rx3. all of these devices may be programmed with the electrical levels required for v.35, v.11, v.10, or v.28 operating modes. in v.35 mode, each transmitter has a common mode pin that is connected to the center of the internal termination. this pin should be bypassed to ground with an external capacitor in order to provide the best possible driver output stage balance. in a system application, the tx1-rx1 pair and tx2-rx2 pair handle the txd-rxd and txc-rxc high-speed interface signals respectively. transceiver tr3 is dedicated to the scte signal for both dce and dte modes of operation. it functions as a receiver for the dte mode and as a transmitter during the dce mode. rtmod2 block rtmod2 contains receivers rx4 and rx5, transmitters tx4 and tx5, and transceiver tr6 which is composed of tx6 and rx6. these devices may be programmed with the electrical levels required for v.11, v.10, or v.28 operating modes. the rx4-tx4 pair are dedicated for rts and cts signals while rx5-tx5 are intended for dtr and dsr signals. transceiver tr3 handles the dcd signal which requires a transmitter in the dce and a receiver in-the- dte mode. rtmod3 block rtmod3 contains transceiver tr7, which is composed of tx7 and rx7, receiver rx8 and transmitter tx8. these devices, which may be programmed with the electrical levels required for v.10, or v.28 operating modes, are intended for the ll, rl and ri signals.
XRT4000 rev. 1.00 - 17 - control block the control block contains the configuration and bias generation circuitry required by rtmod1, rtmod2, and rtmod3. it includes ttl to cmos level shifters for the control signal inputs which have either an internal 20 k w pull- up or pull-down resistor as shown in figure 5 and as described in the pin description. this block also includes a reference voltage source, bias voltage and current generators, and a slew rate control circuit that is used in the v.10 and v.28 modes. the physical interface configuration is done by three control pins called m0, m1 and m2. the logic levels present on these three inputs are internally latched during a positive transition of the latch* signal. the functions of the eight possible combinations of m0, m1 and m2 are described in tables 1 and 2. power requirements table 3, which contains the maximum and minimum peak supply currents for each of the 3 supply voltages, provides the information necessary for determining a system power budget. notice that maximum current is required in the v.11 mode when tx1, tx2, and tx3 are terminated with 100 w . minimum current consumption occurs when none of the transmitters are terminated and the device is not in the v.35 mode. receiver and transmitter specificat ions tables 4 and 5, which are for the XRT4000 receiver and transmitter sections respectively, summarize the electrical requirements for v.35, v.11, v.10, and rs232 interfaces. these tables provide virtually all of the electrical information necessary to describe these 4 interfaces in a concise form.
XRT4000 rev. 1.00 - 18 - control driver/receiver pair and corr esponding signal name - dte mode interface inputs tx1 rx1 tx2 rx2 tx3 rx3 tx4 rx4 tx5 rx5 tx6 rx6 tx7 rx7 tx8 rx8 standard m2 m1 m0 txd rxd scte rxc - txc rts cts dtr dsr - dcd ll tm rl ri 0 0 0 10 10 10 10 off 10 10 10 10 10 off 10 10 off 10 10 v.10 0 0 1 11 11 11 11 off 11 11 11 10 10 off 11 10 off 10 10 eia-530-a 0 1 0 11 11 11 11 off 11 11 11 11 11 off 11 10 off 10 10 eia-530, rs449, v.36 0 1 1 11 11 11 11 off 11 11 11 11 11 off off off off off off x.21 1 0 0 35 35 35 35 off 35 28 28 28 28 off 28 28 off 28 28 v.35 1 0 1 11 11 11 11 off 11 11 11 11 11 off 11 10 off 10 10 reserved 1 1 0 28 28 28 28 off 28 28 28 28 28 off 28 28 off 28 28 rs232 1 1 1 off off off off off off off off off off off off off off off off power down table 1. dte mode - control programm ing for dri ver and receiver mode selection control driver/receiver pair and corr esponding signal name - dce mode interface inputs tx1 rx1 tx2 rx2 tx3 rx3 tx4 rx4 tx5 rx5 tx6 rx6 tx7 rx7 tx8 rx8 standard m2 m1 m0 rxd txd rxc scte txc - cts rts dsr dtr dcd - tm ll ri rl 0 0 0 10 10 10 10 10 off 10 10 10 10 10 off off 10 10 10 v.10 0 0 1 11 11 11 11 11 off 11 11 10 10 11 off off 10 10 10 eia-530-a 0 1 0 11 11 11 11 11 off 11 11 11 11 11 off off 10 10 10 eia-530, rs449, v.36 0 1 1 11 11 11 11 11 off 11 11 11 11 off off off off off off x.21 1 0 0 35 35 35 35 35 off 28 28 28 28 28 off off 28 28 28 v.35 1 0 1 11 11 11 11 11 off 11 11 11 11 11 off off 10 10 10 reserved 1 1 0 28 28 28 28 28 off 28 28 28 28 28 off off 28 28 28 rs232 1 1 1 off off off off off off off off off off off off off off off off power down table 2. dce mode - control programm ing for dri ver and receiver mode selection note: for the above tables: table representation corresponding electrical level type signal 35 v.35 differential 11 v.11 differential 10 v.10 single ended 28 v.28/rs232 single ended
XRT4000 rev. 1.00 - 19 - supply maximum current tx1-tx3 drivers terminated with 100 w in v.11 mode minimum current none of the drivers terminated (non-v.35 mode) vdd (+5v) 160 ma 15 ma vss (-6v) 120 ma 20 ma vpp (+12v) 40 ma 10 ma table 3. maximum and minimum p eak s upply cu rrents v.35 v.11 v.10 rs232 single-ended or differential diff diff single-ended single-ended max signal level 660 mv 6 v 6 v 15 v min signal level 440 mv 300 mv 300 mv 3 v common-mode voltage 2 v 7 v note 1 n/a max signal peak operation 2.66 v 10 v 10 v 15 v max signal peak no damage n/a 12 v 12 v 25 v rin differential 100 w 10% note 2 n/a n/a rin common-mode 150 w 15% n/a n/a n/a dc rin each input to ground > 8k w > 8k w > 8k w 3k w < dc rin < 7 k w clock frequency 20 mhz 20mhz 120khz 256khz table 4. receiver specificat ions note 1 : 7 v on receivers 1-6, not applicable for receivers 7-8 note 2 : 100 to 150 ohms terminated.
XRT4000 rev. 1.00 - 20 - v.35 v.11 v.10 rs232 single-ended or differential diff diff single-ended single-ended max signal level 660 mv rl= 100 w | v0 | < 6 v rl=3900 w 4 < | v0 | < 6 v rl=3900 w 6 v 3000 w < rl < 7000 w min signal level 440 mv rl= 100 w 2v < | vt | >0.5 v0 rl=100 w | vt | > 0.9 v0 rl= 450 w 5 v 3000 w < rl < 7000 w offset voltage n/a | vos | < 3v n/a n/a rout differential 100 w 10% 100 w n/a n/a rout common-mode 150 w 15% n/a n/a n/a rout power off n/a n/a n/a > 300 w output slew rate/tr,tf 20 ns 20 ns 1ms < 30 v/ m s clock frequency 20 mhz 20 mhz 120 khz 256 khz table 5. transmitter specification v.10\v.28 output pulse rise and fall time slew_cntl (pin 47) is an analog output that controls transmitter pulse rise and fall time for the v.10 and v.28 modes. connecting a resistor, rslew, having a value between 0 and 200 k w from this pin to ground controls the rise/fall times for v.10 and the slew rate for v.28 as shown in figures 15 and 16 respectively. high-speed rs232 mode when e_232h* (pin 55) is set to logic 0 in rs232 mode, the transmitters are put is a special high-speed rs232 mode that can drive loads of 3000 w in parallel with 1000pf at speeds up to 256 khz. power down mode all transmitters and receivers may be powered down by either setting the pins for control bits m0, m1 and m2 to logic 1 or by leaving them open. internal cable terminations XRT4000 has fully integrated receiver and transmitter cable terminations for high speed signals (rxd, txd, rxc, txc, scte). therefore, no external resistors and/or switches are necessary to implement the proper line termination. the schematic diagrams given in figures 17 and 18 show the effective receiver and transmitter terminations respectively for each mode of operation. when a specific electrical interface is selected by m0, m1 and m2, the termination required for that interface is also automatically chosen. the XRT4000 eliminates double termination problems and makes point to multipoint operation possible in the v.11 mode by providing the option for disabling the internal input termination on high speed receivers. glitch filters occasional extraneous glitches on control/handshake signal inputs such as cts, rts, dtr and dsr can have damaging effects on the integrity of a connection. the XRT4000 is equipped with lowpass filters on the input of each of the receivers for the control and handshake signals. these filters eliminate glitches which are narrower than 10 m s. the user may disable these filters by setting en_fltr to logic 0.
XRT4000 rev. 1.00 - 21 - clock inversion transmit clock signal, txc, has an inversion option for both dte and dce modes of operation. the user can invert the polarity of the txc by setting ckinv* to logic 0. in the dte mode, the incoming txc signal from the line will be inverted before it is routed to the system. in dce mode, the incoming txc signal from the system will be inverted before it is sent over the line toward the remote dte. this feature allows a phase correction when there is a long cable delay between the dte and dce. this correction may be necessary in order to obtain the desired clock-to-data phase relationship. data inversion similar to txc, there is a provision in the XRT4000 to invert the txd and rxd signals. once the setting the dtinv* input to logic 0 enables an inverter at the output of rx1 and input of tx1. registered mode of operation the XRT4000 has integrated registers allowing users the option of clocking the values of dsr/dtr and rl/ri signals. this can be done if the registered mode of operation is selected (reg=1). in this case, the values of these signals will be latched on the positive edge of the reg_clk signal. in the normal mode (reg = 0), the registers on the path of the dsr/dtr and rl/ri are bypassed and reg_clk will have no effect. similarly, the outputs of the receivers (rx5 and rx8) can be disabled by setting the en_out* input high. this allows these drivers to be connected directly to a microcontroller bus since they can be enabled during read cycles and disabled in other times. this feature eliminates the need for external registers when a microcontroller is used to control (reading and writing) dsr/dtr and rl/ri signals. loopb acks XRT4000 contains internal logic to place the interface in a loopback mode for test purposes. the loopback feature is supported in both dte and dce modes of operation and it can be invoked by setting the lp* input at logic 0. possible loopback implementations are depicted in the scenarios located at the end of this document.
XRT4000 rev. 1.00 - 22 - 10 100 1 10 3 1 10 100 1 10 3 r (k ohms) v.10 rise time (us) figure 15. v.10 rise time as a function of rslew 10 100 1 10 3 0.01 0.1 1 10 r (k ohms) v.28 slew rate (v/us) figure 16. v.28 slew rate o ver 3 v output range with 3 k w in parallel with 2500 pf load as a function of rslew
XRT4000 rev. 1.00 - 23 - echoed clock the XRT4000 can interface with serial controllers which have two or three clock pins. furthermore, it can handle interfaces (e.g. x.21) which have only one clock. information contained in the pin description for the ec* and 2ck/3ck* pins shows how the user can select the number of available clocks by applying the appropriate logic levels to these inputs. self-contained dte loopb ack testing equipment having a dte interface obtains timing information from another interface (dce). rxc and txc are clocks which are sourced by the dce. a dte device uses them to clock data in/out of the interface. the scte clock is generated by dte using txc or rxc which are originated in the dce. in summary, a dte equipment is a timing slave. occasionally it is beneficial to conduct testing of a dte interface without connecting it to its dce counterpart. lack of a synchronization source will make the standalone testing of dte equipment not possible. the XRT4000 has an on-board oscillator which can be used as a timing source while the dce connection is missing. this feature allows users to conduct loopback testing on isolated equipment with a dte interface. this mode is invoked if en_osc* is set to logic 0. this connects an internally generated clock signal (32 khz - 64 khz) to the rx2d/rx3d output. a standalone system test may be performed by combining this feature with the appropriate loopback mode. operat ional scenarios visualizing features such as clock/data inversion, echoed clock, and loopbacks, in dte and dce modes makes configuring the XRT4000 a non-trivial task. a series of 48 system level application diagrams located at the end of the data sheet called scenarios assist users in understanding the benefits of these different features. the internal XRT4000 connections required for a particular scenario are made through mux1 and mux2 that are shown on the block diagrams given in figures 2 and 3 respectively. table 6 contains the signal routing information versus control input logic level for mux1 and table 7 contains similar information for mux2.
XRT4000 rev. 1.00 - 24 - applications information traditional interfaces either require different transmitters and receivers for each electrical standard, or use complicated termination switching methods to change modes of operation. mechanical switching schemes, which are expensive and inconvenient, include relays, and custom cables with the terminations located in the connectors. electrical switching circuits using fets are difficult to implement because the fet must remain off when the signal voltage exceeds the supply voltage and when the interface power is off. the XRT4000 uses innovative, patented circuit design techniques to solve the termination switching problem. this device includes internal circuitry that may be controlled by software to provide the correct terminations for v.10 (rs423), v.11 (rs422), v.28 (rs232), and v.35 electrical interfaces. the schematic diagrams given in figures 17 and 18 conceptually show the switching options for the high-speed receiver input and transmitter output terminations respectively. additionally, tables 4 and 5 provide a summary of receiver and transmitter specifications respectively for the different electrical modes of operation. v.10 (rs423) interface figure 19 shows a typical v.10 (rs423) interface. this configuration uses an unbalanced cable to connect the transmitter txa output to the receiver rxa input. the b outputs and inputs that are present on the differential transmitters and receivers contained in the XRT4000 are not used. the system ground provides the signal return path. the receiver input resistance is 10 k w nominal and no other cable termination is normally used for the v.10 mode. v.11 (rs422) interface figure 11 shows a typical v.11 (rs422) interface. this configuration uses a balanced cable to connect the transmitter txa and txb outputs to the receiver rxa and rxb inputs respectively. the XRT4000 includes provisions for adding a 125 w terminating resistor for the v.11 mode. although this resistor is optional in the v.11 specification, it is necessary to prevent reflections that would corrupt signals on high- speed clock and data lines. the differential receiver input resistance without the optional termination is 20 k w nominal. v.28 (rs232) interface figure 19 shows a typical v.28 (rs232) interface. this configuration uses an unbalanced cable to connect the transmitter txa output to the receiver rxa input. the b outputs and inputs that are present on the differential transmitters and receivers contained in the XRT4000 are not used. the system ground provides the signal return path. the receiver b input is internally connected to a 1.4 v reference source to provide a 1.4 v threshold. the receiver input resistance is 5 k w nominal and no other cable termination is normally used for the v.28 mode. v.35 interface figure 21 shows a typical v.35 interface. this configuration uses a balanced cable to connect the transmitter txa and txb outputs to the receiver rxa and rxb inputs respectively. the XRT4000 internal terminations meets the following v.35 requirements. the receiver differential input resistance is 100 w 10 w and the shorted-terminal resistance (rxa and rxb connected together) to ground is 150 w 15 w . the transmitter differential output resistance is 100 w 10 w and the shorted-terminal resistance (txa and txb connected together) to ground is 150 w 15. the junction of the 3 resistors (cmtx) on the transmit termination is brought out to pins 76 and 81 for tx1 and tx2 respectively. figure 21 shows how capacitor c having a value of 100 to 1000 pf bypasses this point to ground to reduce common mode noise. this capacitor shorts current caused by differential driver rise and fall time or propagation delay miss-match directly to ground. if it was not present, the flow of this current through the 125 w resistor to ground would cause common mode voltage spikes at the txa and txb outputs.
XRT4000 rev. 1.00 - 25 - receiver r1 20 s1 rxxa to rxxb r3 85 r4 30 r6 125 s3 r2 20 s2 r4 30 r8 10k s4 r10 4k r11 6k r9 4k r12 6k mode switches s1 s2 s3 s4 v.35 closed closed open open v.11 terminated open open closed open v.11 unterminated open open open open v.10 open open open open v.28 open open open open figure 17. receiver termination txxa txxb s1 r1 50 r3 125 s2 r2 50 mode switches s1 s2 v.35 closed closed v.11/v.10/v.28 open open
XRT4000 rev. 1.00 - 26 - figure 18. transmitter termination figure 19. typical v.10 or v.28 interf ace (r1 = 10 k w in v.10 and 5 k w in v.28) figure 20. typical v.11 interf ace (terminat ion resistor, r1, is opt ional.) figure 21. typical v.35 interface note: all resistors shown above are internal to the XRT4000.
XRT4000 rev. 1.00 - 27 - scenario number logic l evel applied to control input name/pin number signal source for output name/pin number dce/ dte* ec* 2ck/ 3ck* lp* ck inv* dt inv* en _osc* rx1d tx1b-tx1a rx2d tx2b-tx2a rx3d tr3b-tr3a 39 42 65 22 67 68 66 100 77,78 93 80,79 90 88,87 10101111rx 1b-rx1a tx1d rx2b-rx2a tx2d tr3b-tr3a x 21101111rx 1b-rx1a tx1d rx2b-rx2a tx2d x tx3d 30100111 tx1drx 1b-rx1a tx2d rx2b-rx2a tr3b-tr3a x 41100111 tx1drx 1b-rx1a tx2d rx2b-rx2a x tx3d 50101011rx 1b-rx1a tx1d rx2b-rx2a tx2d (tr3b-tr3a)* x 61101011rx 1b-rx1a tx1d rx2b-rx2a tx2d x (tx3d)* 70100011 tx1drx 1b-rx1a tx2d rx2b-rx2a (tr3b-tr3a)* x 81100011 tx1drx 1b-rx1a tx2d rx2b-rx2a x (tx3d)* 90111111rx 1b-rx1a tx1d rx2b-rx2a x tr3b-tr3a x 101111111rx 1b-rx1a tx1d tx3d tx2d x tx3d 110110111 tx1drx 1b-rx1a tx2d x tr3b-tr3a x 121110111 tx1drx 1b-rx1a tx2d tx3d x tx3d 130111011rx 1b-rx1a tx1d rx2b-rx2a x (tr3b-tr3a)* x 141111011rx 1b-rx1a tx1d tx3d tx2d x (tx3d)* 150110011 tx1drx 1b-rx1a tx2d x (tr3b-tr3a)* x 161110011 tx1drx 1b-rx1a tx2d tx3d x (tx3d)* 1701x1111rx 1b-rx1a tx1d rx2b-rx2a x rx2b-rx2a x 1811x1111rx 1b-rx1a tx1d tx2d tx2d x x 1901x0111 tx1drx 1b-rx1a tx2d x tr3b-tr3a x 2011x0111 tx1drx 1b-rx1a tx2d rx2b-rx2a x x 2101x1011rx 1b-rx1a tx1d rx2b-rx2a x (rx2b-rx2a)* x 2211x1011rx 1b-rx1a tx1d (tx2d)* tx2d x x 2301x0011 tx1drx 1b-rx1a tx2d x (rx2b-rx2a)* x 2411x0011 tx1d note 1 tx2d tx2d x x 250001111rx 1b-rx1a tx1d rx2b-rx2a tr3b-tr3a tr3b-tr3a x 261001111rx 1b-rx1a tx1d rx2b-rx2a tx3d x tx3d 270000111 tx1drx 1b-rx1a tr3b-tr3a rx2b-rx2a tr3b-tr3a x 281000111 tx1drx 1b-rx1a tx3d rx2b-rx2a x tx3d 290001011rx 1b-rx1a tx1d rx2b-rx2a (tr3b-tr3a)* (tr3b-tr3a)* x 301001011rx 1b-rx1a tx1d rx2b-rx2a tx3d x (tx3d)* 310000011 tx1drx 1b-rx1a (tr3b-tr3a)* rx2b-rx2a (tr3b-tr3a)* x 321000011 tx1drx 1b-rx1a tx3d rx2b-rx2a x (tx3d)* 330011111rx 1b-rx1a tx1d rx2b-rx2a x tr3b-tr3a x 341011111rx 1b-rx1a tx1d tx3d tx3d x tx3d 350010111 tx1drx 1b-rx1a tr3b-tr3a x tr3b-tr3a x 361010111 tx1drx 1b-rx1a tx3d tx3d x tx3d 370011011rx 1b-rx1a tx1d rx2b-rx2a x (tr3b-tr3a)* x 381011011rx 1b-rx1a tx1d tx3d tx3d x (tx3d)* 390010011 tx1drx 1b-rx1a (tr3b-tr3a)* x (tr3b-tr3a)* x 401010011 tx1drx 1b-rx1a tx3d tx3d x (tx3d)* 4100x1111rx 1b-rx1a tx1d rx2b-rx2a x rx2b-rx2a x 4210x1111rx 1b-rx1a tx1d tx3d tx3d x x 4300x0111 tx1drx 1b-rx1a rx2b-rx2a x rx2b-rx2a x 4410x0111 tx1drx 1b-rx1a tx3d tx3d x x 4500x1011rx 1b-rx1a tx1d rx2b-rx2a x (rx2b-rx2a)* x 4610x1011rx 1b-rx1a tx1d (tx3d)* tx3d x x 4700x0011 tx1drx 1b-rx1a rx2b-rx2a x rx2b-rx2a x 4810x0011 tx1d note 1 tx3d tx3d x x xxxxx0 1 invert invertunchangedunchangedunchangedunchanged 0 1 x 0 x x 0 unchanged unchanged unchanged unchanged 32-64 khz unchanged 0 0 x 0 x x 0 unchanged unchanged 32-64 khz unchanged 32-64 khz unchanged table 6. mux1 connection table table entries are inputs to mux1. column headings are outputs. signal names ending with a or b are analog inputs or outputs.
XRT4000 rev. 1.00 - 28 - signal names ending with d are digital inputs or outputs. * indicates signal complement. x is dont care. note 1 : refer to figure 22 located on the next page for signal definition. figure 22. signal definition for scenario number 48 scenario number control input/ pin number signal source for output name/pin number dce/ dte* lp* rx4d tx4b-tx4a rx5d tx5b-tx5a rx67d tr6b-tr6a tr7 39 22 48 15,16 41 18,17 40 38,37 35 1 0 0 tx4d rx4b-rx4a tx5d tr6b-tr6a tx5d x tx76d 2 0 1 rx4b-rx4a tx4d rx5b-rx5a tx5d tr6b-tr6a x tx76d 3 1 0 tx4d rx4b-rx4a tx76d rx5b-rx5a tr7 rx5b-rx5a x 4 1 1 rx4b-rx4a tx4d rx5b-rx5a tx5d tr7 tx76d x table 7. mux2 connection table table entries are inputs to mux2. column headings are outputs. signal names ending with a or b are analog inputs or outputs. signal names ending with d are digital inputs or outputs.
XRT4000 rev. 1.00 - 29 - operat ing modes for the xrt 4000 device the XRT4000 multiprotocol serial interface device can be configured to operate in a wide variety of modes or scenarios. this document illustrates some of these scenarios and provides the reader with the following information associated with each of these scenarios. which pins (on the dce mode XRT4000 and dte mode XRT4000 devices) are used to propagate various data or clock signals. which signals are to be used when operating the XRT4000 devices in the differential or single-ended modes. how does one configure the dce mode and dte mode XRT4000 device to operate in these scenarios. notes: 1. the line signals are drawn with both a solid line and a dashed line. both lines are used to transmit and receive differential mode signals. however, the solid line indentifies the signal that should be used, when operating the transmitter in the single-ended mode. 2. each scenarios includes a table that indicates how to configure the XRT4000 device into each of these modes, by specifying the appropriate logic states for ec*, 2ck/3ck*, lp*, ckinv*, dtinv*, and en_osc*. 3. in all, 48 scenarios have been defined for the XRT4000 device. currently, this document only lists a subset of these scenarios. further versions of the XRT4000 data sheet will include this information for all 48 scenarios.
XRT4000 rev. 1.00 - 30 - scenarios 1 & 2 hdlc (r) hdlc (l) t4000 (dte) t4000 (dce) rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 75 82 90 93 100 97 98 96 95 87 88 79 80 78 77 100 93 84 82 75 78 77 79 80 87 88 96 95 97 98 txd scte txc rxc rxd options dte normal 3 clocks no loopback no invert dce echo mode 2 clocks loopback invert 1 clock (x.21) input pin settings (scenarios 1 & 2) t4000 (dte) t4000 (dce) pin number name state pin number name state 39 dce/dte* 0 39 dce/dte* 1 42 ec* 1 42 ec* 1 65 2ck/3ck* 0 65 2ck/3ck* 0 22 lp* 1 22 lp* 1 67 ckinv* 1 67 ckinv* 1 68 dtinv* 1 68 dtinv* 1 66 en_osc* 1 66 en_osc* 1
XRT4000 rev. 1.00 - 31 - scenario 3 hdlc (r) hdlc (l) t4000 (dte) t4000 (dce) rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 75 82 90 93 100 97 98 96 95 87 88 79 80 78 77 100 93 84 82 75 78 77 79 80 87 88 96 95 97 98 txd scte txc rxc rxd options dte normal 3 clocks no loopback no invert dce echo mode 2 clocks loopback invert 1 clock (x.21) input pin settings (scenario 3) t4000 (dte) t4000 (dce) pin number name state pin number name state 39 dce/dte* 0 39 dce/dte* 1 42 ec* 1 42 ec* 1 65 2ck/3ck* 0 65 2ck/3ck* 0 22 lp* 0 22 lp* 1 67 ckinv* 1 67 ckinv* 1 68 dtinv* 1 68 dtinv* 1 66 en_osc* 1 66 en_osc* 1
XRT4000 rev. 1.00 - 32 - scenario 4 hdlc (r) hdlc (l) t4000 (dte) t4000 (dce) rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 75 82 90 93 100 97 98 96 95 87 88 79 80 78 77 100 93 84 82 75 78 77 79 80 87 88 96 95 97 98 txd scte txc rxc rxd options dte normal 3 clocks no loopback no invert dce echo mode 2 clocks loopback invert 1 clock (x.21) input pin settings (scenario 4) t4000 (dte) t4000 (dce) pin number name state pin number name state 39 dce/dte* 0 39 dce/dte* 1 42 ec* 1 42 ec* 1 65 2ck/3ck* 0 65 2ck/3ck* 0 22 lp* 1 22 lp* 0 67 ckinv* 1 67 ckinv* 1 68 dtinv* 1 68 dtinv* 1 66 en_osc* 1 66 en_osc* 1
XRT4000 rev. 1.00 - 33 - scenario 5 hdlc (r) hdlc (l) t4000 (dte) t4000 (dce) rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 75 82 90 93 100 97 98 96 95 87 88 79 80 78 77 100 93 84 82 75 78 77 79 80 87 88 96 95 97 98 txd scte txc rxc rxd options dte normal 3 clocks no loopback no invert dce echo mode 2 clocks loopback invert 1 clock (x.21) input pin settings (scenario 5) t4000 (dte) t4000 (dce) pin number name state pin number name state 39 dce/dte* 0 39 dce/dte* 1 42 ec* 1 42 ec* 1 65 2ck/3ck* 0 65 2ck/3ck* 0 22 lp* 1 22 lp* 1 67 ckinv* 0 67 ckinv* 1 68 dtinv* 1 68 dtinv* 1 66 en_osc* 1 66 en_osc* 1
XRT4000 rev. 1.00 - 34 - scenario 6 hdlc (r) hdlc (l) t4000 (dte) t4000 (dce) rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 75 82 90 93 100 97 98 96 95 87 88 79 80 78 77 100 93 84 82 75 78 77 79 80 87 88 96 95 97 98 txd scte txc rxc rxd options dte normal 3 clocks no loopback no invert dce echo mode 2 clocks loopback invert 1 clock (x.21) input pin settings (scenarios 1 & 2) t4000 (dte) t4000 (dce) pin number name state pin number name state 39 dce/dte* 0 39 dce/dte* 1 42 ec* 1 42 ec* 1 65 2ck/3ck* 0 65 2ck/3ck* 0 22 lp* 1 22 lp* 1 67 ckinv* 1 67 ckinv* 0 68 dtinv* 1 68 dtinv* 1 66 en_osc* 1 66 en_osc* 1
XRT4000 rev. 1.00 - 35 - scenario 7 hdlc (r) hdlc (l) t4000 (dte) t4000 (dce) rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 75 82 90 93 100 97 98 96 95 87 88 79 80 78 77 100 93 84 82 75 78 77 79 80 87 88 96 95 97 98 txd scte txc rxc rxd options dte normal 3 clocks no loopback no invert dce echo mode 2 clocks loopback invert 1 clock (x.21) input pin settings (scenarios 7) t4000 (dte) t4000 (dce) pin number name state pin number name state 39 dce/dte* 0 39 dce/dte* 1 42 ec* 1 42 ec* 1 65 2ck/3ck* 0 65 2ck/3ck* 0 22 lp* 0 22 lp* 1 67 ckinv* 0 67 ckinv* 1 68 dtinv* 1 68 dtinv* 1 66 en_osc* 1 66 en_osc* 1
XRT4000 rev. 1.00 - 36 - scenario 8 hdlc (r) hdlc (l) t4000 (dte) t4000 (dce) rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 75 82 90 93 100 97 98 96 95 87 88 79 80 78 77 100 93 84 82 75 78 77 79 80 87 88 96 95 97 98 txd scte txc rxc rxd options dte normal 3 clocks no loopback no invert dce echo mode 2 clocks loopback invert 1 clock (x.21) input pin settings (scenario 8) t4000 (dte) t4000 (dce) pin number name state pin number name state 39 dce/dte* 0 39 dce/dte* 1 42 ec* 1 42 ec* 1 65 2ck/3ck* 0 65 2ck/3ck* 0 22 lp* 1 22 lp* 0 67 ckinv* 1 67 ckinv* 0 68 dtinv* 1 68 dtinv* 1 66 en_osc* 1 66 en_osc* 1
XRT4000 rev. 1.00 - 37 - scenarios 9 & 10 hdlc (r) hdlc (l) t4000 (dte) t4000 (dce) rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 75 82 90 93 100 97 98 96 95 87 88 79 80 78 77 100 93 84 82 75 78 77 79 80 87 88 96 95 97 98 txd txc rxc rxd options dte normal 3 clocks no loopback no invert dce echo mode 2 clocks loopback invert 1 clock (x.21) input pin settings (scenarios 9 & 10) t4000 (dte) t4000 (dce) pin number name state pin number name state 39 dce/dte* 0 39 dce/dte* 1 42 ec* 1 42 ec* 1 65 2ck/3ck* 1 65 2ck/3ck* 1 22 lp* 1 22 lp* 1 67 ckinv* 1 67 ckinv* 1 68 dtinv* 1 68 dtinv* 1 66 en_osc* 1 66 en_osc* 1
XRT4000 rev. 1.00 - 38 - scenario 12 hdlc (r) hdlc (l) t4000 (dte) t4000 (dce) rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 75 82 90 93 100 97 98 96 95 87 88 79 80 78 77 100 93 84 82 75 78 77 79 80 87 88 96 95 97 98 txd txc rxc rxd options dte normal 3 clocks no loopback no invert dce echo mode 2 clocks loopback invert 1 clock (x.21) input pin settings (scenario 12) t4000 (dte) t4000 (dce) pin number name state pin number name state 39 dce/dte* 0 39 dce/dte* 1 42 ec* 1 42 ec* 1 65 2ck/3ck* 0 65 2ck/3ck* 1 22 lp* 1 22 lp* 0 67 ckinv* 1 67 ckinv* 1 68 dtinv* 1 68 dtinv* 1 66 en_osc* 1 66 en_osc* 1
XRT4000 rev. 1.00 - 39 - scenario 13 hdlc (r) hdlc (l) t4000 (dte) t4000 (dce) rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 75 82 90 93 100 97 98 96 95 87 88 79 80 78 77 100 93 84 82 75 78 77 79 80 87 88 96 95 97 98 txd txc rxc rxd options dte normal 3 clocks no loopback no invert dce echo mode 2 clocks loopback invert 1 clock (x.21) input pin settings (scenario 13) t4000 (dte) t4000 (dce) pin number name state pin number name state 39 dce/dte* 0 39 dce/dte* 1 42 ec* 1 42 ec* 1 65 2ck/3ck* 1 65 2ck/3ck* 1 22 lp* 1 22 lp* 0 67 ckinv* 0 67 ckinv* 1 68 dtinv* 1 68 dtinv* 1 66 en_osc* 1 66 en_osc* 1
XRT4000 rev. 1.00 - 40 - scenario 14 hdlc (r) hdlc (l) t4000 (dte) t4000 (dce) rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 75 82 90 93 100 97 98 96 95 87 88 79 80 78 77 100 93 84 82 75 78 77 79 80 87 88 96 95 97 98 txd txc rxc rxd options dte normal 3 clocks no loopback no invert dce echo mode 2 clocks loopback invert 1 clock (x.21) input pin settings (scenario 14) t4000 (dte) t4000 (dce) pin number name state pin number name state 39 dce/dte* 0 39 dce/dte* 1 42 ec* 1 42 ec* 1 65 2ck/3ck* 1 65 2ck/3ck* 1 22 lp* 1 22 lp* 1 67 ckinv* 0 67 ckinv* 0 68 dtinv* 1 68 dtinv* 1 66 en_osc* 1 66 en_osc* 1
XRT4000 rev. 1.00 - 41 - scenario 16 hdlc (r) hdlc (l) t4000 (dte) t4000 (dce) rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 75 82 90 93 100 97 98 96 95 87 88 79 80 78 77 100 93 84 82 75 78 77 79 80 87 88 96 95 97 98 txd txc rxc rxd options dte normal 3 clocks no loopback no invert dce echo mode 2 clocks loopback invert 1 clock (x.21) input pin settings (scenario 16) t4000 (dte) t4000 (dce) pin number name state pin number name state 39 dce/dte* 0 39 dce/dte* 1 42 ec* 1 42 ec* 1 65 2ck/3ck* 1 65 2ck/3ck* 1 22 lp* 1 22 lp* 0 67 ckinv* 1 67 ckinv* 0 68 dtinv* 1 68 dtinv* 1 66 en_osc* 1 66 en_osc* 1
XRT4000 rev. 1.00 - 42 - scenario 17 & 18 hdlc (r) hdlc (l) t4000 (dte) t4000 (dce) rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 75 82 90 93 100 97 98 96 95 87 88 79 80 78 77 100 93 84 82 75 78 77 79 80 87 88 96 95 97 98 txd rxc rxd options dte normal 3 clocks no loopback no invert dce echo mode 2 clocks loopback invert 1 clock (x.21) input pin settings (scenario 17 & 18) t4000 (dte) t4000 (dce) pin number name state pin number name state 39 dce/dte* 0 39 dce/dte* 1 42 ec* 1 42 ec* 1 65 2ck/3ck* x 65 2ck/3ck* x 22 lp* 1 22 lp* 1 67 ckinv* 1 67 ckinv* 1 68 dtinv* 1 68 dtinv* 1 66 en_osc* 1 66 en_osc* 1
XRT4000 rev. 1.00 - 43 - scenario 20 hdlc (r) hdlc (l) t4000 (dte) t4000 (dce) rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 75 82 90 93 100 97 98 96 95 87 88 79 80 78 77 100 93 84 82 75 78 77 79 80 87 88 96 95 97 98 txd rxc rxd options dte normal 3 clocks no loopback no invert dce echo mode 2 clocks loopback invert 1 clock (x.21) input pin settings (scenario 20) t4000 (dte) t4000 (dce) pin number name state pin number name state 39 dce/dte* 0 39 dce/dte* 1 42 ec* 1 42 ec* 1 65 2ck/3ck* x 65 2ck/3ck* x 22 lp* 1 22 lp* 0 67 ckinv* 1 67 ckinv* 1 68 dtinv* 1 68 dtinv* 1 66 en_osc* 1 66 en_osc* 1
XRT4000 rev. 1.00 - 44 - scenario 21 hdlc (r) hdlc (l) t4000 (dte) t4000 (dce) rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 75 82 90 93 100 97 98 96 95 87 88 79 80 78 77 100 93 84 82 75 78 77 79 80 87 88 96 95 97 98 txd rxc rxd options dte normal 3 clocks no loopback no invert dce echo mode 2 clocks loopback invert 1 clock (x.21) input pin settings (scenario 21) t4000 (dte) t4000 (dce) pin number name state pin number name state 39 dce/dte* 0 39 dce/dte* 1 42 ec* 1 42 ec* 1 65 2ck/3ck* x 65 2ck/3ck* x 22 lp* 1 22 lp* 1 67 ckinv* 0 67 ckinv* 1 68 dtinv* 1 68 dtinv* 1 66 en_osc* 1 66 en_osc* 1
XRT4000 rev. 1.00 - 45 - scenario 22 hdlc (r) hdlc (l) t4000 (dte) t4000 (dce) rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 75 82 90 93 100 97 98 96 95 87 88 79 80 78 77 100 93 84 82 75 78 77 79 80 87 88 96 95 97 98 txd rxc rxd options dte normal 3 clocks no loopback no invert dce echo mode 2 clocks loopback invert 1 clock (x.21) input pin settings (scenario 22) t4000 (dte) t4000 (dce) pin number name state pin number name state 39 dce/dte* 0 39 dce/dte* 1 42 ec* 1 42 ec* 1 65 2ck/3ck* x 65 2ck/3ck* x 22 lp* 1 22 lp* 1 67 ckinv* 1 67 ckinv* 0 68 dtinv* 1 68 dtinv* 1 66 en_osc* 1 66 en_osc* 1
XRT4000 rev. 1.00 - 46 - scenario 23 hdlc (r) hdlc (l) t4000 (dte) t4000 (dce) rx1 tx1 rx2 tx2 rx3 tx3 rx2 tx2 rx1 tx1 txd scte txc rxc rxd txd scte txc rxc rxd 75 82 90 93 100 97 98 96 95 87 88 79 80 78 77 100 93 84 82 75 78 77 79 80 87 88 96 95 97 98 txd rxc rxd options dte normal 3 clocks no loopback no invert dce echo mode 2 clocks loopback invert 1 clock (x.21) input pin settings (scenario 23) t4000 (dte) t4000 (dce) pin number name state pin number name state 39 dce/dte* 0 39 dce/dte* 1 42 ec* 1 42 ec* 1 65 2ck/3ck* x 65 2ck/3ck* x 22 lp* 0 22 lp* 1 67 ckinv* 0 67 ckinv* 1 68 dtinv* 1 68 dtinv* 1 66 en_osc* 1 66 en_osc* 1

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